Interference Aware workload colocation in Hypersclae datacenters (Research Intern), [Facebook Inc, Summer 2019-Summer 2020]
Datacenters today process billions of requests per day and are convergent points for processing, storing, and distributing a colossal quantity of data. They use massive amounts of state-of-the-art computation units, which consist of heterogeneous compute, memory, network, and other resources. Workload diversity and workload resource usage patterns lead to the under-utilization of these resources. We explore a dynamic, low overhead, and highly scalable framework that utilizes workload and hardware characterization complemented with network traffic and power usage information to balance resource contention and provide better resource utilization.


Managing application performance and system efficiency via resource management (Research Assistant),
[University of Rochester, Summer 2018]
Modern NUMA architectures give rise to the challenges of bringing data close to compute for maximum performance. To achieve overall system performance, applications can be migrated closer to the data while respecting and tweaking the application parallelism and recognizing resource sweet-spot without compromising SLAs or QoS constraints. Presented poster in PPoPP 2019.


Cache replacement policy based expected reuse intervals (Research Assistant), [University of Rochester, Fall 2019]
We propose a statistical method to keep track of instruction pointer-based access reuse interval distribution and use this information to predict the  Least Expected Use (LEU) blocks for replacement.


Bloom filter based prefetcher throttling mechanism to improve performance (Fall Co-Op), [AMD Inc, Fall 2018]
We proposed bloom filters to throttle prefetchers to reduce cache pollution and improve prefetch accuracy. Also, look at state-of-the-art prefetchers with a modified mechanism for performance improvement.



Identifying thread/process data sharing patterns for NUMA aware colocation (Research Assistant), [University of Rochester, Spring 2017-Spring 2018]

In order to bring data close to compute, this project aimed to use Intel PEBS, Linux perf, and Bloom filters to identify thread sharing patterns and mitigate these issues by co-location within a single socket or distribution across sockets.

BDD based synthesis of Boolean functions using memristor IMPLY Logic (Research Intern), [Indian Institute of Technology (IIT), Kharagpur, Summer 2014]

Used Binary Decision Diagrams (BDD) to represent Boolean circuits and represented the nodes of the circuit with nodes being represented as a 2-to-1 Multiplexer implemented using Memristor IMPLY Logic. This resulted in a paper in IEEE International Design and Test Symposium (IDTs).
 

To see more or discuss possible work let's talk >>